Item transport deviation detection device

ABSTRACT

A device and method for detecting interruptions or deviations of normal item transport in an item transport pathway wherein a signal indicative of an interruption or deviation is generated whenever a transported item takes longer than a predetermined time to be transported between two stations in the pathway, or whenever an item remains longer than a predetermined time at the second of the stations, the two consecutive time conditions being imposed by the same timing element.

Hated States atent [i 3,626,956

[72] Inventor Oran A. J. Sauder [56 References Cited [21] A I No lg 'ggUNITED STATES PATENTS {22] Augdl 1970 2,963,293 [2/1960 Klein 340/259[45] Patented Dec 14:1971 9/1965 Hanchett,.lr. 340/259 I. ,1 8/1967 M le,1 340/259 [73] Ass'gnee Eggfi'gg' 3,341,837 9/1967 wzihihgtbn 340/259Primary ExaminerJohn W. Caldwell Assistant Examiner-J. Michael BobbittArromeys- Kenneth L. Miller and Edwin WI Uren [54] ERANSPORT DEVIATIONDETECTION ABSTRACT: A device and method for detecting interruptions DE Dor deviations of normal item transport in an item transport sclmmssrawmg pathway wherein a signal indicative of an interruption or [52]U.S.Cl 340/259, deviation is generated whenever a transported item takes271/57, 340/309?) longer than a predetermined time to be transportedbetween [51] Int. Cl ..G08b 21/00 two stations in the pathway. orwhenever an item remains [50] Field of Search 340/259, longer than apredetermined time at, the second of the stations, 309.3,42l,420; 271/57the two consecutive time conditions being imposed by the same timingelement.

GEFIERATE A SIGIiAL COIFICIDEFIT WITH THE LEADIRG EDGE OF A DOCLEZGEFJTAT POIBIT A mmm A TIEiII'GG SEGUEIAGE TIMING TIAiIIIG SEGUEIGGE SEQUENCENOT EXPIRED EXPIRED GEAERATE A SIGHAL GEAHWE HE DURATIOM INTERRUPTSIGAAL I DF DOCUMENT TRAVEL L sEoumcE AT LEADIAG EDGE OF SIGI IAL DELAYSIGIIIAL REIPIITIATE TIAIIIIG SEQUEFIGE GOIIICIDEiIT WITH LEADIIIG EDGEDE DELAYED SIGNAL TIMING TIIAIIIG SEQUENCE SEQUEEGE NOT EXPIRED EXPIREDEND REIIIITIATED GEFIERATE mmg SEQUENCE II-ITERIIUPT SIGFIAL ATTRAILIFIG EDGE OF DELAYED SIGNAL PATENTEO 0E8 I #811 SHEET 1 OF 3 FIGI.

I GENERATE A SIGNAL COINCIDENT WITH THE LEADING EDGE OF A DOCUMENT ATPOINT A INITIATE ATIMING SEQUENCE TIMING SEQUENCE NOT EXPIRED TIMINGSEQUENCE EXPIRED GENERATE A SIGNAL FOR THE DURATION OF DOCUMENT TRAVELPAST POINT B GENERATE INTERRUPT SIGNAL END TIMING DELAY SIGNAL SEQUENCEAT LEADING EDGE OF SIGNAL REINITIATE TIMING SEQUENCE COINCIDENT WITHLEADING EDGE OF DELAYED SIGNAL TIMING SEQUENCE NOT EXPIRED TIMINGEXPIRED SEQUENCE END REINITIATED TIMING SEQUENCE INTERRUPT SIGNALGENERATE AT TRAILING EDGE OF DELAYED SIGNAL INVENTOR. ORAN A. J. SAUDER.

AGENT.

PATENTEI] DEC! 4 I97! SHEET 2 [IF 3 INTERRUPT SIGNAL RESETABLE TIMINGCIRCUIT C RCU T B STABILEL PATENTEU m1 4 an SHEET 3 BF 3 FIG.4.

VOUT

ITEM TRANSPORT DEVIATION DETECTION DEVICE BACKGROUND The inventionrelates generally to item transport monitoring systems and specificallyto circuits for detecting jams in document passageways ofdocument-handling equipment.

In the art of high-speed handling of thin, pliable items such as paperdocuments, precision is required in driving and maneuvering the itemsthrough various guides and passageways of the handling equipment. Theoccurrence of any malfunction in the document transport section of suchdocument-handling equipment generally leads to serious consequences, aswhen a check inadvertently becomes lodged in the transport passage of acheck reader/sorter and causes a large number of following checks to bedestroyed, disfigured or misread.

A common method of preventing such adverse consequences of transportmalfunctions is to provide means for detecting an initial interruptionor deviation in document flow, and to shut off the document-drivingmechanism before a large number of documents are destructively impelledinto the obstructed area. With the document-driving apparatus sodisabled, the dislodged or obstructing document may be removed before aserious jam condition develops.

The antecedents of the present invention serve to detect interruptionsin normal document flow, and upon such detection, to generate a signalthat is effective to initiate a shutting down of the document-drivingmechanism. Known prior art jam detection devices commonly combine twoswitching members such as phototransistors at selected predeterminedlocations in the document passageway, to detect the presence ofdocuments at these specific selected locations. Document travel timebetween these two phototransistors is measured by means of circuitrycombining a flip-flop and a timing circuit such as a resettable delay.If the measured time exceeds a predetermined time, either a coincidencedetection circuit coupled to the flip-flop and the resettable delay, orthe delay itself, serves to generate an electrical signal indicative ofan interrupted or deviated document flow condition between the twophototransistors. Prior art jam detection devices accordingly impose oneprecedent condition to the recognition of an interrupted or delayeddocument; that is, that the document travel between two fixed positionsin a predetermined time. It is obvious that the greater the number ofinterruption detection circuits that are provided in the documentpassageway, in order to increase the probability of detecting anydocument delay occurrences, the greater the number of stations andphototransistors that would need to be used, and the greater the numberof precedent conditions that would need to be imposed. A highly reliabledetection system of the prior art type would accordingly require morespace than is normally available, and be exceedingly costly to build.

SUMMARY OF THE INVENTION It is generally an object of the presentinvention to provide a reliable document flow interruption detectionsystem that requires a minimum of space in the transport area, and aminimum number of circuit components per precedent condition imposed.

The invention accomplishes this and other objects by enabling a singletiming element or resettable delay to measure the duration of documenttravel in two contiguous segments of a transport pathway, a precedentcondition being imposed for each segment. The time required for theleading edge of a document to be transported between a first and asecond point in the transport pathway, and the time interval between thepassage of the leading edge and the trailing edge of the document pastthe second of the points are each measured by the timing element. Ifeither measured time is greater than the predetermined times, asestablished by the timing element, a signal is generated indicating adeviated document transport condition.

The invention provides that the timing element is reset after measuringthe transport duration of the leading edge of a document between thefirst and second points in the transport pathway, and that an itemdetection signal from the second switching member is delayed in order toreset the timing element for measuring the interval of time between thepassage of the leading and trailing edges of the document past thesecond switching member.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing themethod by which a deviated condition of item flow is detected;

FIG. 2 is a block diagram showing the basic composition of a preferreditem transport deviation detection device;

FIG. 3 is a circuit diagram of the transport deviation detection device;

FIG. 4 is a timing diagram illustrating the operation of the transportdeviation detection circuit under normal item flow conditions; and

FIG. 5 is a timing diagram illustrating the operation of the transportdeviation detection circuit when an item fails to traverse the secondswitching member in the predetermined time interval.

DETAILED DESCRIPTION To facilitate a more complete understanding of thesubject invention, a specific example or preferred embodiment willhereinafter be described in connection with the drawings. For thepurpose of illustration, the jam detection device will be described inconjunction with a check sorter, although it is to be understood thatthe fundamental concept of the invention may be applied with equalsuccess to any type of documenthandling equipment. The check sorterenvisioned has a pathway for guiding checks past a series of pockets.Associated with each pocket along the pathway is a diverting gate whichis selectively activatable by control circuitry to intercept a checktraveling at a high rate of speed down the pathway and to direct it intoan associated pocket. Although one or more jam detection devices may bepositioned anywhere along the transport path of the envisioned checksorter, for our present purposes it is assumed a single such device isso positioned as to detect a deviation in document flow past a divertinggate, the probability of a document jam at such location beingrelatively high due to the variable forces that are applied to adocument in this area.

The concept of jam detection that is embodied in the present inventionimposes two precedent conditions under which a jam or interruption ofdocument flow is detected. The conditions are:

I. That a check travel from a predetermined first point (point A)positioned anteriorly of the gate to a second point (point B) positionedposteriorly of the gate in a prescribed time;

2. That the trailing edge of a check departs from point B in aprescribed time interval following the arrival of its leading edge atpoint B.

Should either of these conditions not obtain during the flow of a checkdown the transport pathway, the device would generate an interruptsignal effective either for shutting off the document transportmechanism or for alerting the operator to the time deviation at theassociated gate.

The method by which the aforementioned precedent conditions are imposedis illustrated in the flow chart of FIG. 1. First, a switching meansdetects the leading edge of a document as it passes point A andgenerates an electrical signal that begins a timing sequence. Theduration of the timing sequence is a period of time slightly greaterthan the time required for the leading edge of a check to pass point Aand arrive at point B under normal document transport conditions. If theduration of the timing sequence expires before the leading edge of thecheck arrives at point B, an interrupt signal is generated indicatingthat the check travel has been slower than normal or totally interruptedbetween point A and point B. If the check arrives at point B before thetiming sequence has expired, switching means at point B will serve togenerate an electrical pulse during the period that the check passes infront of the switching means at point B. The electrical signal from theswitching means at point B is delayed for a period of time that isrelatively short compared with its normal duration, thereby permittingthe timing circuit that was used to initiate the timing sequence to bereset so that it can be reinitiated at the leading edge of the delayedsignal from the switching means at point B. If the reinitiated timingsequence expires before the trailing edge of the delayed signal, aninterrupt signal is generated indicating that the check has not passedpoint B within the prescribed time. if the check has passed point Bbefore the timing sequence has expired the check has arrived in itspocket within the normal and prescribed time.

The circuit components that are combined to carry out theabove-described process are shown in FIG. 2. A first switching means 11located at point A in the document transport pathway is electricallyconnected to a bistable circuit 12. A second switching means 13 locatedat point B in the pathway is also electrically connected to the bistablecircuit 12. The first switching means 11 activates an electrical signalwhen the leading edge of a check enters its associated position in thetransport pathway, or, in other words, passes point A. The secondswitching means 13 responds electrically to the passage of the entirelength of the check past its associated position in the pathway, or inother words, past point B, thus generating an electrical signal thatbegins with the passage of the leading edge of the check by point B. Theelectrical signal from the first switching means ll triggers thebistable circuit 12 to its Q state. Following the electrical signal fromthe first switching means 11, a signal from the second switching means13 triggers the flip flop to its 6 state. The output from the secondswitching means 13 at point B in the pathway is also electricallyconnected to a delay circuit 14. The output from the delay 14 iselectrically connected to the bistable circuit 12 for triggering thecircuit to the Q state. The state of the bistable circuit 12 iselectrically connected to a resettable timing circuit 15 that serves togenerate an electrical signal when the Q state of the bistable circuit12 is maintained for longer than a predetermined time.

As shown in FIG. 3 phototransistors l6 and 17 have been chosen as theswitching means at points A and B in the transport pathway. As describedabove. it is not necessary that the first switching means 11 of thefirst phototransistor l6 electrically respond to the full length ofabypassing check, but only to the leading edge. A phototransistornevertheless has been chosen as the preferred switching means at pointA, as it achieves the desired operational characteristics while itsextraneous characteristic (i.e., that it activates a pulse for the fullduration of a bypassing check) has no deleterious effect upon itsrequired characteristics in the circuit design.

The bistable circuit 12 of the jam detection device as illustrated inFIG. 3 includes a common RS flip-flop having two cross-coupled NOR-gatesl8 and 19. A first of the NOR-gates I8 is electrically connected to anappropriately amplified collector output of the first phototransistor l6and to the output of the second NOR-gate 19. The second NOR-gate 19 ofthe flip-flop is electrically connected with the output of the firstNOR-gate l8 and an appropriately amplified collector output of thesecond phototransistor 17. The bistable circuit 12 has a third NOR-gate20 that electrically gates the output from the second NOR-gate l9 and adelayed output from the second phototransistor 17. The delay element 14of the invention is a capacitor 21 having its positive plateelectrically connected to the second phototransistor 17 output and itsnegative plate to ground.

The resettable timing circuit 15, as shown in FIG. 3 has an NPN controltransistor 22 connected at its base to the output From the thirdNOR-gate 20 of the bistable circuit 12. The colector of the controltransistor 22 is electrically connected to :he emitter ofa PNP outputtransistor 23. A positive voltage source +V is electrically connected ata common node to the collector of the control transistor 22 and to theemitter of the output transistor 23. The base element of the outputtransistor is electrically connected to the positive side of the diode24. The negative side of the diode 24 is connected to a positive voltagesource V The value of V in volts is less than the value of V,. A timingcapacitor 25 has its positive plate connected at the common node withthe collector of the control transistor 22 and the emitter of the outputtransistor 23. The negative plate of the timing capacitor iselectrically connected to ground.

OPERATION The operation of the subject device will first be describedunder normal operating conditions; that is, when the document or checktravels past point A and point B in the transport pathway in a normalpredetermined time interval. With reference to the timing diagram ofFIG. 4, a document passing the first phototransistor at point A in thecheck transport pathway will cause the first phototransistor to generatea pulse (PT having a leading edge at I and a trailing edge atj2.Assuming the output of the second NOR-gate I9 is low at time I, theoutput of the first NOR-gate 18 of the bistable circuit 12 goes low atthe leading edge of the output pulse from the first phototransistor. Theoutput (V from the third NOR-gate 20 of the bistable circuit 12 goes lowat the leading edge of the output (PT,) from the first phototransistor16 thus beginning a timing sequence. At the trailing edge of the pulsefrom the first phototransistor 16 no other changes in states occur. Whena document proceding along the pathway of the check sorter reaches thesecond phototransistor 17 at point B in the pathway, the secondphototransistor generates a pulse (PT,). This pulse occurring at I isdelayed for a short period of time by the delay capacitor 21 thusallowing the output (V from the third NOR-gate 20 to go high until thedelay capacitor charges to a predetermined voltage at which time theoutput from the third NOR gate again goes low. It is this shortpositive-going pulse occurring at the leading edge of the output fromthe second phototransistor that permits the timing circuit 15 to reset.When the output (V,,,) from the third NOR-gate 20 of the bistablecircuit 12 is high the base of the control transistor 22 is high therebybiasing the transistor in a conducting state and dropping the voltage atthe common node. As the emitter of the output transistor 23 iselectrically connected to the common node, the low voltage at the nodeserves to bias the output transistor in a nonconducting state. When theoutput (V from the third NOR-gate 20 goes low the control transistor 22is biased to a nonconducting state. As both the control and the outputtransistors are nonconducting, the voltage across the timing capacitor25 increases with time. If it attains a high enough voltage before thecontrol transistor 22 again turns on and discharges the timing capacitor25 the output transistor will turn on, thus generating an interruptsignal (V When the normal flow of documents past the twophototransistors l6 and 117 takes place the period of time in which theoutput from the third NOR-gate 20 remains low is less than the timerequired for the timing capacitor 25 to charge to a sufi'icient voltagevalue to bias the output transistor 23 in a conducting state. When thesecond phototransistor 17 at point B in the transport path ofa checkgenerates a pulse, a short positive going pulse is displayed at theoutput of the third NOR-gate 20 of the bistable circuit 12. Thispositive-going pulse biases the control transistor 22 to a conductingstate which allows the timing capacitor 25 to discharge. After a shortdelay the output from the third NOR- gate 20 of the bistable circuit 12again goes low and the charging of the timing capacitor 25 or timingsequence begins again. If the time between the leading edge ofa checkand the trailing edge of a check passing the second phototransistor 17is less than the time required for the timing capacitor 25 of theresettable timing circuit 15 to charge to an extent that the outputtransistor 23 will be biased in a conducting state, the output voltagefrom the output transistor will remain low until some abnormally slowdocument in the flow either takes longer than the charging time totravel from the first to the second phototransistor or to traverse thesecond phototransistor.

In the latter case, for example, the output (PTg) from the secondphototransistor 17 would occur for longer than the duration 1 to 1 inFIG. 4. As shown in the timing diagram of FIG. 5, the trailing edge ofthe output pulse (PT,) from the second phototransistor 17 has notoccurred, at time meaning that the document passing in front of it hasbeen somehow slowed from its normal rate of movement while passing pointB. After the delay has been reset at time I the timing capacitor 25 ofthe resettable timing circuit is again begins to charge. At time 1-, thesecond phototransistor l7 still has not detected the trailing edge ofthe document passing thereby and the timing capacitor has charged to avoltage that biases the output transistor 23 in a conducting state.Under these conditions an output pulse (v or interrupt signal from thecollector of the output transistor 23 indicates a deviation from normaldocument flow.

What is claimed is:

1. ln document handling apparatus having a pathway for guidingtransported documents, a method for detecting a deviation in normaldocument transport between a first and a second stationary point in thepathway comprising the steps of:

generating a first electrical signal coincident with the leading edge ofa document passing said first stationary point, initiating a timingsequence of predetermined duration coincident with said first electricalsignal, generating a second electrical signal for the duration of saiddocument passing said second stationary point,

generating an interrupt signal if the predetermined duration of saidtiming sequence expires before the beginning of said second electricalsignal,

delaying said second electrical signal for a short period of timerelative to the full duration thereof, reinitiating said timing sequencecoincident with the delayed beginning of said second electrical signal,and

generating an interrupt signal if the predetermined duration of saidreinitiated timing sequence expires before the delayed ending of saidsecond electrical signal.

2. ln apparatus for transporting an item along a predetermined pathway,a device for detecting a deviation from a normal rate of item transportcomprising:

first switching means stationed adjacent the pathway for electricallyresponding to the leading edge of an item passing thereby,

second switching means stationed adjacent the pathway at a predetermineddistance in' the direction of item transport from said first switchingmeans, said second switching means being electrically responsive to thepassage of the full length of an item thereby,

means electrically coupled with said second switching means for delayingthe electrical response of said second switching means for asubstantially short duration relative to the duration of the normalelectrical response of said second switching means,

bistable means electrically coupled with said first switching means,said second switching means, and said delaying means for manifesting afirst stable electrical state upon an electrical response from saidfirst switching means, for manifesting a second stable electrical stateupon an electrical response from said second switching means, and foragain manifesting said first stable electrical state for the duration ofthe delayed electrical response from said delaying means, and

timing means electrically coupled with said bistable means forgenerating an electrical signal when said bistable means remains in saidfirst stable electrical state for longer than a predetermined period oftime, whereby said electrical signal indicates a deviation In the rateof normal item transport between said first and said second switchingmeans or past said second switching means.

3. A device as defined by claim 2 wherein said first and said secondswitching means are each characterized by a photoelectric elementstationed on said pathway and a source of light for switching saidelement in response to an item passing thereby.

4. A device as defined by claim 2 wherein said delaying means is acapacitor.

5. A device as defined by claim 2 wherein said bistable means includes aflip-flop switchable by an electrical response from said first switchingmeans to a first electrical state and by an electrical response fromsaid second switching means to a second electrical state, and a NORlogical operator electronically gating said first electrical state withsaid delayed electrical response of said second switching means.

t 8K t i t

1. In document handling apparatus having a pathway for guidingtransported documents, a method for detecting a deviation in normaldocument transport between a first and a second stationary point in thepathway comprising the steps of: generating a first electrical signalcoincident with the leading edge of a document passing said firststationary point, initiating a timing sequence of predetermined durationcoincident with said first electrical signal, generating a secondelectrical signal for the duration of said document passing said secondstationary point, generating an interrupt signal if the predeterminedduration of said timing sequence expires before the beginning of saidsecond electrical signal, delaying said second electrical signal for ashort period of time relative to the full duration thereof, reinitiatingsaid timing sequence coincident with the delayed beginning of saidsecond electrical signal, and generating an interrupt signal if thepredetermined duRation of said reinitiated timing sequence expiresbefore the delayed ending of said second electrical signal.
 2. Inapparatus for transporting an item along a predetermined pathway, adevice for detecting a deviation from a normal rate of item transportcomprising: first switching means stationed adjacent the pathway forelectrically responding to the leading edge of an item passing thereby,second switching means stationed adjacent the pathway at a predetermineddistance in the direction of item transport from said first switchingmeans, said second switching means being electrically responsive to thepassage of the full length of an item thereby, means electricallycoupled with said second switching means for delaying the electricalresponse of said second switching means for a substantially shortduration relative to the duration of the normal electrical response ofsaid second switching means, bistable means electrically coupled withsaid first switching means, said second switching means, and saiddelaying means for manifesting a first stable electrical state upon anelectrical response from said first switching means, for manifesting asecond stable electrical state upon an electrical response from saidsecond switching means, and for again manifesting said first stableelectrical state for the duration of the delayed electrical responsefrom said delaying means, and timing means electrically coupled withsaid bistable means for generating an electrical signal when saidbistable means remains in said first stable electrical state for longerthan a predetermined period of time, whereby said electrical signalindicates a deviation in the rate of normal item transport between saidfirst and said second switching means or past said second switchingmeans.
 3. A device as defined by claim 2 wherein said first and saidsecond switching means are each characterized by a photoelectric elementstationed on said pathway and a source of light for switching saidelement in response to an item passing thereby.
 4. A device as definedby claim 2 wherein said delaying means is a capacitor.
 5. A device asdefined by claim 2 wherein said bistable means includes a flip-flopswitchable by an electrical response from said first switching means toa first electrical state and by an electrical response from said secondswitching means to a second electrical state, and a NOR logical operatorelectronically gating said first electrical state with said delayedelectrical response of said second switching means.